A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories

Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be implemented with multiple small memories, if generated by memory compilers. In this paper we introduce a testability-driven memory optimizer and wrapper generator that generates BISTed embedded memories by using a commercial memory compiler. We describe one of its key components called MORE (for Memory Optimization and REconfiguration). The approach is cost effective for designing embedded memories. By configuring small memory cores into the large one specified by the user and providing the BIST circuits, MORE allows the user to combine the commercial memory compiler and our memory BIST compiler into a cost-effective testability-driven memory generator. The resulting memory has a shorter test time, since the small memory cores can be tested in parallel, so far as the power and geometry constraints are considered. As an example, the test time of a typical 256K 32 memory generated by MORE is reduced by about 75%.